In the past thirty years, VLSICAD (Computer-Aided Design of Very Large-Scale Integrated circuits) has been an enabling force behind the exponential growth of the performance and capacity of integrated circuits according to Moore’s Law. The challenges in continuing this have to a great degree shifted from process and manufacturing technology to design automation. In the last ten years, hierarchical algorithms have been applied with dramatic results to several important areas in VLSICAD, but with relatively little direct transfer of known results in applied math. Moreover, top-down hierarchical methods are facing serious limitations as interconnects and other factors associated with the deep submicron process technologies make high-level design abstraction more and more difficult. Increasingly, multilevel methods are seen as indispensable to scalable solutions, but the associated knowledge seems insufficient to meet the immediate demands of VLSICAD. General examples of such methods include wavelets in signal and image processing, domain decomposition methods in computational fluid dynamics, multigrid in numerical PDE simulation, and fast multipole methods in large-scale particle simulations. The multilevel approach has been successfully applied to several areas of VLSICAD, including circuit partitioning (e.g., the hMETIS package from University of Minnesota), circuit placement (e.g., the PL algorithm from UCLA), and parasitic extraction (e.g., the FASTCAP package from MIT).
We invite mathematicians, computer scientists, and electrical engineers interested in this area to participate. The program includes tutorials in general VLSICAD and combinatorial multilevel algorithms, as well as talks by specialists on state-of-the art solutions to some of the most difficult problems in the field.
Achi Brandt
(Weizmann Institute of Science)
Jason Cong
(UCLA)
Joseph Shinnerl
(UCLA)
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